Coherent digital multifunction processor

ABSTRACT

A coherent digital multifunction processor that is capable of multiple-mode processing and can also perform rapid inter-mode switching. Additionally, while processing data in a given mode, the subject processor is capable of self-synchronization, thereby obviating the requirement for external synchronous devices. The instant processor has a central control which may suitably utilize a general purpose computer in one embodiment. The primary modes of operation of the subject processor are: a pulse doppler acquisition and/or tracking mode, a moving target indicator mode, and an incoherence mode.

S atent [1 1 July 10, 1973 COHERENT DIGITAL MULTIFUNCTION PROCESSORInventors: Adolph M. Chwastyk; Alan M.

lDiamant, both of Silver Spring, Md.

The United States of America as represented by the Secretary of theNavy, Washington, DC.

Filed: Feb. 18, 1972 Appl. No.: 227,586

Assignee:

US. Cl. 343/7.7, 343/5 DP, 343/l7.2 PC, 343/100 CL llnt. Cl. G01s 9/42Field of Search 343/17.2 PC, 7.7, 343/5 DP, 100 CL References CitedUNITED STATES PATENTS Nolen et a1. 343/7.7 X

11/1971 Darlington 343/172 PC 12/1972 Taylor, .lr. 343/77 X PrimaryExaminer-Malcolm F. Hubler Art0rne vR. S. Sciascia and Joseph A. (ook[57] ABSTRACT A coherent digital multifunction processor that is capableof multiple-mode processing and can also perform rapid inter-modeswitching. Additionally, while processing data in a given mode, thesubject processor is capable of self-synchronization,thereby obviatingthe requirement for external synchronous devices. The in stant processorhas a central control which may suit ably utilize a general purposecomputer in one embodiment. The primary modes of operation of thesubject processor are: a pulse doppler acquisition and/or tracking mode,a moving target indicator mode, and an incoherence mode.

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COHERENT DIGITAL MULTIFUNCTION PROCESSOR BACKGROUND OF THE INVENTION Animportant result of the years of experience with radar is therealization that no one combination of transmission pattern and echoprocessing scheme is best for the wide variety of commercial andgovernment radar applications. This is true even for a particular radarhaving a narrowly prescribed mission. The conflicting demands of searchand track operations, the vagaries of weather, chaff and other clutter,the different types of electronic interference, and the many forms ofthe targets of interest all frustrate the search for the best radarsystem even for a specific application.

This situation suggests the need for adaptive radars, single systemswith multiple modes and parameters to deal effectively with the changingtasks and environment. In the past, such systems were not feasiblebecause of the instabilities, timing restrictions, poor reliability, andhigh costs characteristic of analog hardware. As a result, separateradars each with very little flexibility were built to perform thesearch, acquisition, and tracking functions. Today, however, the highspeed, reliability, and low cost of digital microelectronic componentsmake it practical to build digital radar synchronizers and processorsthat do not suffer the restrictions of their analog counterparts. Datacan be integrated or stored for unlimited times without loss.Transmission patterns and receiver delays can be changed withoutswitching components. Size and weight are reduced. Ultimate control canbe performed by a digital general purpose computer thereby enhancing thenatural flexiblity of the digitized radar.

Thus, from the above the need for digital multipurpose radar is madeclear. The need to study the clutter characteristics that must determineits modes and how it is to be programmed for adaptive detection,acquisition, and tracking is also made obvious. To supply these needsthe present invention, a coherent digital multifunction processor,hereinafter referred to as CODIMUP, is provided. Codimup is a digitalsynchronizer-processor (hereafter referred to simply as processor") thatcan be incorporated into many radar defense, traffic control, ormeteorological systems. It is designed specifically to demonstrate thedigital implementation of a processor having several modes and parameteroptions to investigate land and weather clutter properties; to providerapid comparisons of the effectiveness of the waveforms in rejecting themany varieties of clutter; and to determine the criteria for modeselection and threshold setting, based on target and cluttercharacteristics, in an adaptive system.

SUMMARY OF THE INVENTION Codimup has two fundamental processing modes:Moving Target Indication (MTI) and Pulse Doppler (PD). MTl and PDsystems combine the advantage of simple pulse and continuous wave radarsby providing both range and velocity discrimination. A PD or MTItransmission is a set of pulses that are samples of a stable, noise freesine wave; thus the pulses are coherently related. The time of receptionof each echo from a target is proportional to range, and the dopplerfrequency shift on the sine wave samples is proportional to radialvelocity. For example, a frequency analysis of the echoes from a volumecell can reveal an aircraft in land clutter, even though the aircraftcontributes only a small percentage of the total return power.

In the MTI mode, a single notch filter rejects echoes within a band ofclutter frequencies, while passing all those at targer frequencies. Thefiltering is accomplished by a process of cancelling successive echopulses against each other. Phase corrections can be applied to the pulseto center the filter at frequencies other than zero. The uncancelledresidue" signals are from targets moving at velocities outside the MTInotch.

In the PD mode, a set of filters distributes the echo energy intovelocity storage elements or bins", thus performing a spectrum analysison the contents of each volume cell. Each filter is formed by applyingappropriate phase corrections or rotations to the set of received pulseand then integrating the rotated pulses coherently. The process isequivalent to finding the complex discrete Fourier Transform of the echopulses.

While PD and MTI modes both use doppler techniques to help discriminatebetween reflectors, the methods of processing in the two modes aredistinct, causing differences in filter characteristics that influenceperformance in clutter. A major difference is that the MTI mode cancelsand thus rejects signals within the band of clutter frequencies, whilethe PD mode merely segregates that band of frequencies into one or morefilter bins. The effect is that the MTI mode loses a target whosedoppler is within the band of clutter frequencies, while the PD moderetains the target and clutter power in some number of filter bins whichmay be thresholded to detect the target. The MTI mode has the advantageof being faster in processing the returns from a given volume andrequires fewer pulses, making it the logical mode to choose for searchoperations in moderate clutter.

The instant invention is designed to be versatile, provide alternatemodes for changing tasks and environmental conditions. It makes possiblequantitative comparisons of the performance of different waveforms orprocessing techniques in the same target environment. Entirely digital,the subject processor interfaces naturally with a digital computer whichultimately can be programmed to do adaptive mode switching based ontarget-clutter characteristics.

It is an object of this invention to provide a processor that is capableof multiple-mode and intermode processing.

It is another object of this invention to provide a digital processorthat can operate in a coherent fashion.

It is another object of this invention to provide multifunction digitalprocessor that is capable of operating in both pulse doppler acquisitionand tracking modes.

It is another object of this invention to provide a coherent digitalprocessor that is capable of self-synchronization.

It is another object of this invention to provide a coherent digitalmultifunction processor that is capable of operating in a moving targetindicator mode.

These and other objects of the present invention will become betterunderstood when considered with the detailed description and also withthe accompanying drawings.

DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall block diagram of thepresent invention;

FIG. 2 is a block diagram of the sensitivity time control/automatic gaincontrol (STC/AGC) unit;

FIG. 3 is a graph of the possible STC/AGC function;

FIG. 4 is a block diagram of the processor unit of FIG. 1;

FIG. 5 is a chart showing a response curve for the MTI mode withthree-pulse cancellation;

FIG. 6 is a chart showing another response curve for the MTI mode havingstaggered pulse trains;

FIG. 7 is a block diagram of a circuit for processing the response curveof FIG. 6;

FIG. 8 is a chart showing a response curve having various staggerratios;

FIG. 9 is a flow diagram for MTI mode processing in the processor unit;and

FIG. 10 is a flow diagram for PD mode processing in the processor unit.

DETAILED DESCRIPTION OF THE INVENTION Referring now to FIG. 1, there isshown an overall block diagram of a radar system incorporating theCODIMUP processor of the present invention. The transmitter portion ofFIG. 1 includes a programmable frequency generator 10, a fast switchingbinary phase modulator 12, a traveling wave tube (TWT) power amplifier14, a transmit-receive selection circuit 16, and a parabolic dishantenna 18. The receiver system contains a low noise TWT 20, a digitalsensitivity time control/automatic gain control (STC/AGC) circuit 22 anda quadrature homodyne mixer 24. The STC/AGC circuit 22 can be setmanually or by a computer to attenuate strong returns from close inreflectors or to compensate for signals strength fall-off with range.The STC/AGC circuit 22 can be set to give one of five attenuationslopes; zero, linear, square, cube or fourth law. The STC/AGC circuitcan be regulated by a computer to provide automatic gain control in thePD track mode. The STC/AGC circuit 22 will be described in greaterdetail hereinafter. The mixer circuit 24 has two outputs: a bipolarin-phase (I) video output 26 and a quadrature-phase (Q) video output 28.Uncoded bipolar video pulses are match-filtered by means of delay lines30 and 32 and integrators 31 and 33. Coded pulses are compressed byfeeding the output of the delay line circuits 30 and 32 into pulsecompression circuits 34 and 36 respectively, which in one embodimentcould each be a simple resistive decoding circuit. The uncoded outputsof integrators 31 and 33 as well as the coded outputs of pulsecompression circuits 34 and 36 are fed into an A/D converter 38 whoseoutput, in turn, is then fed into a synchronizer/processor (hereinafterreferred to as the processor) 40. A control console 42 is used tomanually designate mode and parameters. Adaptive control is alsopossible because all designations to the processor 40 are made through acomputer control shown in block diagram at 44. Processed data can thenbe transferred from the computer for tracking computations, analysis,and printouts. The processor 40 is an expandable wired-program machinethat performs coherent multiply-add cycles to cpmpute the discreteFourier transform of the echo system signals in the PD mode and to nullthe return of a specific doppler in the MTI modes. The processor 40 alsocontrols waveform generation and all timing.

Incorporated in the Coherent Multifunction Process (CODIMUP) is theabove-mentioned digitally controlled RF attenuator STC/AGC unit 22 forperforming sensitivity time control (STC), automatic gain control (AGC),and manual gain control. STC and manual gain control is in effect duringthe acquisition mode and AGC is in effect during the track mode. TheSTC/AGC unit 22 decreases the attenuation in the RF stage of CODIMUPfrom a maximum range to a minimum range.,The initial attenuation and theslope thereof (either zero, linear, square, cube, or fourth law slopesare selectable. Maual gain control is a special case of the STC mode,namely zero slope, and introduces an attenuation in the front end of theprocessor. During the track mode, the AGC RF attenuation is controlledby the CODIMUP processor.

The digital STC/AGC unit 22 is interfaced with the present invention asis shown in FIG. 2. The STC unit consists of an STC control panel 50, adigital STC/AGC interface circuit 52, PIN modulators 54 and 56 which areeach preceded by low noise TWTs 58 and 60 respectively. The output ofPIN modulator 56 is fed to an output TWT 62 which in turn is fed intothe mixer 24 as shown. The selection of either STC or AGC mode is doneon a dwell-by -dwell basis via an acquisition/track control output 49from the processor 40. In the sTC mode the PIN modulators 54 and 56 aredriven with analog voltage derived from digitally generated sTCfunctions in the digital circuit 52. The STC functions (both slope andinitial value) are selected by the STC control panel 50. A digital worddescribing the functions selected by the STC control panel 50 to thedigital interface 52 is sent to the computer 44 via the processor 40. Inthe AGC mode, the STC control panel 50 is bypassed and a digitalattenuation word is sent directly to the PIN modulators 54 and 56.Samples of the different STC functions are shown in the graph of FIG. 3.

Referring to the processor in more detail, CODIMUP has four major modes:MTI search, PD Acquisition, PD-Track, and Step-Frequency. Each mode hassuboptions: MTI with two, three, or four-pulse coherent cancellation andincoherent integration of the uncancelled residues; choice of MTI pulseweighting constants, incoherent integration with no cancellation for areference or burnthrough mode; PD with or without pulse amplitudeweighting for sidelobe regulation; PD Track with several degrees ofpulse compression for range resolution control; choice among severalpulse repetition frequencies (PRF) and non-uniform or staggered PRFoption to cope with range ambiguities, blind speed, and countermeasures;choices of number of pulses in each transmission; and choice of dwellrate. Mode and parameter selections are made manually or automaticallythru the computer. Manual control independent of the computer is alsopossible.

In MTI mode, the processor is an n-pulse weighted summer with whichbinomial weighting is equivalent to an (nl )-stage cascaded series ofsingle delay-line cancellers. The MTI output is an (N, X l) amplitudematrix of moving target residue signals, where N, is the number ofcontiguous range gates (bins) in the dwell.

In PD mode, the processor computes the complex discrete Fouriertransform of the echo doppler signal. The PD output is an N, X Namplitude matrix of range vs doppler frequency, where N,, is the numberof doppler filters (bins), equal to the number of pulses in atransmission (dwell).

Referring now to FIG. 4 there is shown a block diagram of the processorunit. As previously mentioned, the l and Q bipolar video signalsemergent from the integrators 31 and 33 and the pulse compressioncircuits 34 and 36 of FIG. 1 are digitized by four A/D converters 38.Two of the digital converters are in use for PD acquisition and MTImodes, and all four are used as PD track early and late gates. Theoutput of the A/D converters are all applied to an arithmetic unit 64wherein the incoming video data is sampled at predetermined intervals,converted into the proper format and weighted by vector rotation. Thearithmetic unit receives direction input from a pulse dopplersine/cosine generator unit 66 which, in turn, receives direction fromthe program control register 68. The program control register 68additionally supplied command information to a synchronizer unit 41which inputs to the radar system triggers and gating signals.Additionally, the program control register 68 provides timing andprogram control in unit 70 for associated processor units. After thevideo is sampled, converted and weighed, it is either stored forprocessing at the end of the dwell (if it is one of the PD modes), orimmediately added to a coherent running sum (if it is one of the MTImodes). If the video is to be stored it will be applied to a memory unit72 which receives command information from a memory address unit 74. Ifthe video is to be added to a coherent running sum the output of thearithmetic unit 64 is applied to an arithmetic unit 76 whereinsummation, square root and peak select computations are performed. Theoutput of arithmetic unit 76 is applied simultaneously to the computer44 and to the display and control panel 42. The memory unit 72 is anintegrated circuit random access memory having read or write cycletimes. Within the arithmetic unit 64 are multiply units for complexvector rotations and accumulations. In arithmetic unit 76 square rootsof the sum of the squares by approximation and real accumulations areperformed. The pulse doppler sine/cosine generator unit 66 containscircuits for calculating rotating unit vectors, stepped either uniformlyor by a prestored pattern. The program control register unit 68 directsall transistor-transistor and diode-transistor integrated circuits thatare used in the generator unit 66.

Logically implemented as an expandable, fixed wired program machine, theprocessor is specifically oriented to solving the multiply-add cyclesrequired for compub ing the discrete Fourier transform of eitheruniformly or non-uniformly sampled time series. Programming is done withthe aid of shift registers and logical decision gates for conditionaland loop controls. This design allows any number of non-conflictingmicro-orders to be executed during a single compute cycle.

For coherent processing, the input signals to CODIMUP are quadraturecomponents, labeled l for in-phase and Q for quadrature-phase. Theprocessor performs complex arithmetic by simple multiplications andaccumulations of the quadrature components, each of which is digitallyrepresented by six bits plus sign. The final outputs are bit amplitudes,obtained by taking the square root of the sum of the squares of theprocessed components. The I and Q video signals are sampled very l.6,usecs within a range interval or "window whose variable position andwidth are defined by the starting range R, and the number of range binsNT. Since there are N pulses in a dwell, a total of NN, samples aretaken for processing.

In the MTI modes (i.e. the MTI and MTI the processor is a k-pulseweighted summer, which binomial weighting is equivalent to a (k-l)-state cascaded delay-line vector canceller. The MTI output is a set ofN, amplitudes, resulting from accumulation of K inputs per range bin.With no clutter locking (having the MTI notch automatically track theclutter means velocity), the first MTI null centers at zero doppler.

The MTI, mode takes the square root of the sum of the squares of the Iand 0 components of each sample and accumulates the resulting amplitudesof N samples in each range bin. This is simply incoherent integration ofdetected video and serves as'a"burnthroug'h" mode for maximumdetectability in heavy jamming. It also serves as a reference mode bywhich performance in the MTI modes can be evaluated.

In the MTI every sample is coherently subtracted from the sample that isreceived during the next pulse repetition interval. The differences orresidues are incoherently accumulated for a total of N pulses per rangebin processed The first I-channel sample can be represented by E(t) E,sin (21rf t +41) where f is the doppler frequency and (1),, 411R /A isthe phase shift due to two-way range. If successive returns are highlycorrelated, the second I-sample is E(t T) ==E, sin [2w F (t+ T) qSo]where T l/f, is the pulse period, andf, is the pulse frequency. TheI-residue is Note that unity weight is given to each sample. Similarly,the Q-residue is 2E; sin s/ cos 2%: wf /f, a, 1r/2).

The square root of the sum of the squares ofl and Q is the amplitudeThis is identical to the response of a single-stage delay line vectorcanceller.

The pulse weights of E(t) and E (T+ t) for the twopulse canceller were+1, I. For a k-pulse canceller having response identical to a cascaded(k-lJ-stage delay line canceller, the pulse weights are the binomialcoefficients of (l x)". By combining the weighted pulses, as shown abovefor the two-pulse case, the general power response for a k-pulsecanceller is seen to be S /S, 2 sin (rrf lf This equation gives the MTIpower gain with respect to doppler frequency. It shows that stationaryclutter is completely rejected, but so are targets at the blind speeds"occurring atf,,/f l, 2, etc. Since perfect sample-to-sample amplitudestability was assumed, the equation gives the maximum realizable MTIrejection and gain. The average value of this function can be expressedas the series 1/[(S,,/s, 1 m [m(m-l)/2!] [m(ml) (m2)/3!] where m k-l.(Note that this series terminates after m 1 terms, and the final term is1.). Thus the MTI power gain, averaged over all doppler frequencies, forthe k=2, 3, and 4 modes are Increasing the value of k improves clutterrejection, but also increases the width of the blind speed regions. FIG.5 is the response curve for a three-pulse canceller connected to ans-band search radar operating at 3000 MHZ with an f, of 1870 Hz (maximumunambiguous range 50 miles). The abscissa is calibrated in miles perhour. Assuming equally probable radial velocities from to 627 mph, thereis a 32 percent chance for a target response to be more than 13 db belowpeak.

Since the locations of the nulls are a function off reposition of theresponse curves for two or more pulse trains with differentf s wouldgive a curve with filled in nulls. Just such a composite response can beobtained by alternating or staggering" the length of the period Tbetween pulses. FIG. 6 is an example ofa staggered pulse train havingtwo periods, T1 and T2. If the stagger ratio" Tl/TZ is the ratio of twointegers a/b, then the first fully blind doppler frequency isf blind a/Tb/T Stagger ratios must be chosen with care, since intolerably deepnulls in the response can occur before the first complete null. FIG. 7shows how a twoperiod staggered train may be processed by utilizing apair of delay lines 80 and 82, binomial weighting circuits 84, 86 and88, and an adder circuit 90. FIG. 8 gives the response curves for Kratios from 0.6 to 0.9. The first blind frequency in the range of thegraph is at f 4/ for a/b 0.6. In the s-band radar example given above,this corresponds to a radial velocity of 836 mph, as compared to 209 mphfor the uniform f case.

Refer to FIG. 9 for the basic MTI flow diagram. The MTl mode is choseneither manually or by computer program control. The MTI power k is thenumber of pulses cancelled. The choices of k are l, 2, 3, and 4. (Thek=l mode is actually simple integration of pulse amplitudes). Associatedwith each choice of k is a set of weighting constants w; wherej is thepulse number within the set of k pulses. The set w, k is adjustable bycontrol panel toggle switches, and can be set to be binomialcoefficients. As an example, assume MTI is the chosen mode, withbinomial weights l 2, 1), number of pulses N=33, and number of rangebins N, =63. Starting at T the echo from each pulse is sampled every1.6,u. sec, for a range resolution of 240 meters. At each range bin r,the I and Q returns from the first three pulses are multiplied by l, 2,and 1. The weighted components are added algebraically, completecancellation occurring only if there are no amplitude or phasedifferences among the three vectors. Following the coherentcancellation, the amplitude of the cancellation residue is found bycalculating the square root of the sum of the squares of the l and Qresidues. This amplitude is stored. Then the next three pulses areprocessed in the same way, and the second residue amplitude is added tothe first one. This continues for 11 sets of 3 pulses each, or the totalof 33 pulses in the dwell. The final memory content is the result ofincoherent integration of 11 residue amplitudes of a threepulse vectorcanceller for each of 63 range bins.

The coherent part of the processing can be expressed y The incoherentpart, or, post-detection integration, can be expressed by n/Ir r 2 ran Qwhere m is the cancellation pulse-set number.

The square root of the sum of the squares operation is implemented bythe approximation (a b")" x (Larger of lal a lbl V2 (Smaller of l l a ll (For ease in following, the flow diagram of FIG. 9 shows alloperations occurring serially. However, parallel operations go on inCODIMUP wherever it is practical to implement them. For instance, theMTI incoherent loop actually is entered while the j=k coherent loop isbeing processed).

Computer transfers take place at the end of each dwell. The maximumintegrated residue and its memory location are transferred along withthe starting range R,,. The memory location and R pinpoint the preciserange bin of the maximum for target detection and tracking. At thebeginning of the next dwell, updated R is transferred from the computerto the processor. Presently, no tracking has been programmed, and thecomputer transfers manually-updated range information to CODIMUP.

If an MTI dump is called for, CODIMUP is stepped thru all four MTImodes, and the integrated residue amplitudes from the fourdwells aretransferred to the computer memory. The dwell outputs can then be storedon magnetic tape for future analysis, or for an immediate printout. I

In the PD mode, the processor calculates the discrete Fourier transformof the returns from N pulses at each of N, range bins. The output is anNXN, amplitude matrix of doppler-range cells. Doppler frequency isrelated to radial velocity by W C/2 f l fo where c is the speed of lightin m/sec,f,, is the dopplcr frequency in Hz,f is the transmitterfrequency in Hz, and v, is the target radial velocity in m/sec.Therefore, the PD output is a velocity analysis of the returns from therange window.

Within a range bin, the series of returns from N pulses are actuallysamples of the doppler signal from the interval. By taking the Fouriertransform of those samples, the doppler spectrum is derived, but notwithout ambiguities caused by the discrete sampling. The ambiguity ismore of a problem in PD than in MTI because of the conflicting demandsof unambiguous doppler and range. The minimum sampling frequencynecessary to measuref,, with no ambiguity in an l-Q system is f, =f, l/Tf,,,

For unambiguous range response,

where 1- is the pulse duration. Notice that reducing T to increasedoppler coverage results in decreased maximum unambiguous range.

The content of a range-doppler resolution cell can be represented as N-ldm l lLr' 'jodml 2 where I and Q are the rotated I and Q components.FIG. is the flow diagram for the PD processing.

SUMMARY OF THE INVENTION In summary, therefore, what has been disclosedis a digital processor-synchronizer which accepts various encodedwaveforms and performs coherent processing in any of a number of modesduring any one dwell. The modes include MT] and PD processing. Apostdetection integration capability allows for noncoherent processing.A small, general purpose computer controls the processor and allowsrapid mode and radar parameter change. The combination of the aboveelements provides a system with automatic adaptive response to whateverclutter and noise environment is encountered.

We claim:

1. In a coherent, multifunction processor for accepting encodedwaveforms and for performing coherent processing thereupon, thecombination comprising;

variable attenuation means receiving and attenuating said encodedwaveforms whenever a predetermined signal strength is received therein;

mixer means responsive to said attenuated encoded signal for dividingsaid attenuated encoded signal into coded and uncoded in-phase andquadraturephase video components;

means operably connected to said mixer means for match-filtering saiduncoded video components; means operably connected to said mixer meansfor compressing said coded video components; converting means receivingsaid filtered uncoded video components and said compressed coded videocomponents for converting all of said components into a predetermineddata format; signal synchronizing means responsive to the output of saidconverting means for providing signal-type identification of saidconverted signal;

signal processing means receiving the output of said signalsynchronizing means for extracting the information content from saidsynchronized signal; and mode control means operably connected to saidsignal synchronizing means and to said signal processing means forcontrolling the operation of said N l 2 N-l dm n',ll.r 11 0 signalsynchronizing processing means, wherein the manner of said control isdependent upon the characteristics of said encoded waveforms.

2. The processor as claimed in claim 1 wherein signal-typeidentification is either in a moving target indicator mode or in a pulsedoppler mode and further wherein said manner of control of said modecontrol means is also determined by said signal-type identification.

3. The processor as claimed in claim 2 wherein said variable attenuationmeans is a digital sensitivity time control/automatic gain controlcircuit having a plurality of attenuation slopes.

4. The processor as claimed in claim 3 wherein said converting means isan analog-to-digital conyerter.

5. The processor as claimed in claim 4 wherein said sensitivity timecontrol/automatic gain control circuit is regulated by said mode controlmeans.

6. The processor as claimed in claim 5 wherein said match-filter meanscomprises delay line circuit means receiving the output of said mixingmeans for delaying in time said mixed signal; and

integrating circuit means responsive to the output of said delay linecircuit means for integrating said dc layed output signal. 7. Theprocessor as claimed in claim 6 wherein said compressing means comprisesvideo delay line means operably connected to said mixing means, fordelaying in time said coded video components, said video delay linemeans pro ducing therefrom a coded pulse output; and

means receiving said coded pulse output of said video delay line meansfor compressing in time said coded pulse output.

8. The processor as claimed in claim 7 wherein said pulse compressionmeans is a resistive decoding circuit.

9. The processor as claimed in claim 8 wherein said signal processingmeans is an expandable wiredprogram circuit means for performingcoherent multiply-add cycles in the computation of discrete Fouriertransforms of the echo signals in the pulse doppler mode and to null thereturn of a specific doppler response in the moving target indicator.

10. The processor as claimed in claim 9 wherein said signal processingmeans comprises:

arithmetic means receiving the output of said analogto-digitalconverting means for sampling said incoming video data at predeterminedintervals, for converting said sampled data into the proper format andfor weighing said converted data by vector rotation;

sine/cosine generating means operably connected to said arithmetic meansfor providing direction input to said arithmetic means during said pulsedoppler mode; and

program control register means responsive to said sine/cosine generatingmeans for directing said sine/cosine generating means and for supplyingcommand information to the signal processing unit.

11. The processor as claimed in claim 10 wherein said signal processingmeans further comprises central computer control means for storing theprocessed video at the end of a dwell if said mode control means is in apulse doppler mode or for adding the processed video to a coherentrunning sum if said mode control means is in said moving targetindicator mode.

12. The processor as claimed in claim 11 wherein said arithmetic meansperforms summation, square root and peak select computations when saidprocessed video is to be added to a coherent running sum.

l 1r a

1. In a coherent, multifunction processor for accepting encodedwaveforms and for performing coherent processing thereupon, thecombination comprising; variable attenuation means receiving andattenuating said encoded waveforms whenever a predetermined signalstrength is received therein; mixer means responsive to said attenuatedencoded signal for dividing said attenuated encoded signal into codedand uncoded in-phase and quadrature-phase video components; meansoperably connected to said mixer means for match-filtering said uncodedvideo components; means operably connected to said mixer means forcompressing said coded video components; converting means receiving saidfiltered uncoded video components and said compressed coded videocomponents for converting all of said components into a predetermineddata format; signal synchronizing means responsive to the output of saidconverting means for providing signal-type identification of saidconverted signal; signal processing means receiving the output of saidsignal synchronizing means for extracting the information content fromsaid synchronized signal; and mode control means Operably connected tosaid signal synchronizing means and to said signal processing means forcontrolling the operation of said signal synchronizing processing means,wherein the manner of said control is dependent upon the characteristicsof said encoded waveforms.
 2. The processor as claimed in claim 1wherein signal-type identification is either in a moving targetindicator mode or in a pulse doppler mode and further wherein saidmanner of control of said mode control means is also determined by saidsignal-type identification.
 3. The processor as claimed in claim 2wherein said variable attenuation means is a digital sensitivity timecontrol/automatic gain control circuit having a plurality of attenuationslopes.
 4. The processor as claimed in claim 3 wherein said convertingmeans is an analog-to-digital converter.
 5. The processor as claimed inclaim 4 wherein said sensitivity time control/automatic gain controlcircuit is regulated by said mode control means.
 6. The processor asclaimed in claim 5 wherein said match-filter means comprises delay linecircuit means receiving the output of said mixing means for delaying intime said mixed signal; and integrating circuit means responsive to theoutput of said delay line circuit means for integrating said delayedoutput signal.
 7. The processor as claimed in claim 6 wherein saidcompressing means comprises video delay line means operably connected tosaid mixing means, for delaying in time said coded video components,said video delay line means producing therefrom a coded pulse output;and means receiving said coded pulse output of said video delay linemeans for compressing in time said coded pulse output.
 8. The processoras claimed in claim 7 wherein said pulse compression means is aresistive decoding circuit.
 9. The processor as claimed in claim 8wherein said signal processing means is an expandable wired-programcircuit means for performing coherent multiply-add cycles in thecomputation of discrete Fourier transforms of the echo signals in thepulse doppler mode and to null the return of a specific doppler responsein the moving target indicator.
 10. The processor as claimed in claim 9wherein said signal processing means comprises: arithmetic meansreceiving the output of said analog-to-digital converting means forsampling said incoming video data at predetermined intervals, forconverting said sampled data into the proper format and for weighingsaid converted data by vector rotation; sine/cosine generating meansoperably connected to said arithmetic means for providing directioninput to said arithmetic means during said pulse doppler mode; andprogram control register means responsive to said sine/cosine generatingmeans for directing said sine/cosine generating means and for supplyingcommand information to the signal processing unit.
 11. The processor asclaimed in claim 10 wherein said signal processing means furthercomprises central computer control means for storing the processed videoat the end of a dwell if said mode control means is in a pulse dopplermode or for adding the processed video to a coherent running sum if saidmode control means is in said moving target indicator mode.
 12. Theprocessor as claimed in claim 11 wherein said arithmetic means performssummation, square root and peak select computations when said processedvideo is to be added to a coherent running sum.